1. Field of the Invention
The present invention relates to the design and manufacture of complex devices, including integrated circuits; and more particularly to estimation of manufacturing yield based upon layout design data and defect models.
2. Description of Related Art
Manufacturing yield is a measure of the number of defective devices made during a manufacturing process which also yields good devices. Improvements in manufacturing yield lead to increases in manufacturing efficiency and reduced costs. In the integrated circuit manufacturing, yields are affected by so-called extra material defects caused by foreign particles, like dust, which settle on a layer of the device, and cause short circuits, open circuits, or other types of defects in the devices being manufactured. Defects can also be caused by missing material, and other things.
In the design of complex devices like integrated circuits, it is desirable to predict the yield of the device under design, so that design improvements may be made if needed to improve the yield. Background concerning yield prediction procedures is found in U.S. Pat. No. 6,178,539 B1, which is incorporated by reference as if fully set forth herein.
Because designs for integrated circuits are so complex, yield predictions are typically made for very localized or isolated portions of the layout. Using these portions, a yield curve as a function of defect size is calculated to model device failure rates given defect size, distribution and density. Sometimes, a two-dimensional equivalent yield map is produced for a small portion of a layout, which characterizes the yield by mapping locations on the layout having structures that have higher probability of suffering defects that affect yield. The two-dimensional calculation is very expensive in terms of computational resources, even for small areas. Two-dimensional calculations for the entire layout of a full chip are impractical using reasonably available computers.
Accordingly, there is a need for a method and system for two-dimensional yield map calculation that can be practically applied to large layouts, including full-chip layouts in integrated circuit design.